3D IC (three-dimensional integrated circuit) technology is a processing technique to perform three-dimensional spatial stacking of the multi-layered IC. Compared to traditional 2D IC, 3D IC allows more elements being positioned more adjacent to one another on the chip, so that the distance among the signal lines of the elements can be significantly decreased, which further improves the lag effect of signal transmission and power consumption. Generally, 3D IC process adopts TSV (Through Silicon Via) which includes the steps of forming holes on the wafer, then filling a conductive material (such as copper, polycrystalline silicon, and tungsten) into the holes to form conductive channels, and finally thinning the wafer or dies and stacking and joining the same for forming the 3D IC chip.
In addition to producing TSV within the dies for connecting the dies of different functions, a technique which uses interposer along with TSV technology to join different chips for forming the 3D IC is also provided. Nowadays, development of 3D IC interposer technology principally focuses on the silicon and glass substrates. The silicon substrate has good thermal conductance (K: ˜140 W/mK), and when it is used as the interposer of the multi-chip stack in the 3D IC process, the possibility that the elements fail due to heat accumulation under high-power operation can be lowered. However, since the energy band gap of the silicon substrate (1.1 eV/300 K) is not large, there is a concern of electrical leakage if the silicon substrates are applied for the electrical elements of thinned chip stack with higher voltage. To solve this problem, a technique of forming an oxide layer on the silicon substrate is developed in order to enhance the effect of insulation. Although this technique can improve electrical leakage of the interposer, heat dissipating ability of the elements is lowered and the manufacturing cost is raised. To enhance competitive capability of the product by lowering the manufacturing cost of the interposer, a lot of manufacturers start to use glass (silicon dioxide) substrates as the interposer substrate. Although the glass substrate interposer has preferable insulation, is not expensive, and is much more available and currently becomes one of the materials of the interposer developed by the manufactures, for the applications in relevant products with miniaturized, multi-functional, and high efficient demands, the glass substrate interposer has low thermal conductance (K: ˜1.5 W/mK), and thus the chip modules have poor heat dissipating effect, easily resulting in gradual accumulation of heat source at the interface of the multi-layered stack of the chips and causing thermal failure of the elements. Therefore, the glass substrates are only suitable for the application of the products with lower power in the 3D IC process.
To solve the problem of electrical leakage and heat dissipation of the interposer, polycrystalline aluminum nitride substrates with low cost are now aggressively developed. Since aluminum nitride has good thermal conductance (K: 170˜320 W/mK) and larger energy band gap (energy band gap: 6.015 eV), it can provide better thermal conductivity and insulation. Besides, since aluminum nitride has higher dielectric coefficient, the caused dielectric loss will be comparatively low, and thus the cross-talk effect between the electrically conductive lines can be mitigated.
Currently, the TSV process for the interposer is mainly to include the steps of defining the positions of the vias by the lithography technique, using the cured photoresist film or the metal coating layer as the etching barrier layer, and performing dry etching to form the vias. However, polycrystalline aluminum nitride is a material of ceramics with 11.5 eV of Al—N bonding energy. Thus, the etching rate of polycrystalline aluminum nitride substrate is much lower than that of the currently used silicon substrate, and it is required to strengthen conditions of the etching process and increase the thickness of the barrier layer to achieve the desired etching depth. With regard to the lithography process, resolution of the currently used dry type photoresist is insufficient, and the wet type photoresist, in order to form the small-sized pattern, would lead to the result that the thickness of the photoresist is too thin to deposit the etching barrier layer with sufficient thickness. Moreover, since the selectivity of the barrier layer to the aluminum nitride substrate is not high, it is a challenge to from micro holes or trenches with high aspect ratio. Further, the thickness of the barrier layer is positively proportional to the thickness of the photoresist in the lithography process, therefore the TSV process for forming the pattern with high aspect ratio will encounter the problem that the resolution conflicts with the etching depth. The prior arts do not provide any breakthrough for this problem. Furthermore, the lithography process includes complicated steps, and it is inevitable to require much time and labor in the TSV process.
With regard to the process of forming the aluminum nitride interposer, the TSV process is one of the key developing processes. Developing the TSV process for the aluminum nitride substrate interposer mainly lies in the technique of forming the micro holes with high aspect ratio (blind holes or through holes). If the aluminum nitride substrates can be used in the 3D IC process and the metallized through holes with high aspect ratio can be efficiently formed, thermal accumulation produced by the stacked multi-chip module system at high power can be effectively reduced, and the reliability of the system can be enhanced and the signal noises can be decreased. Evidently, it is the critical technique of developing the ceramic interposer.
Therefore, there is a need for the industry to develop a method of forming a pattern with high aspect ratio on the polycrystalline aluminum nitride substrate, which helps to efficiently form the metallized through holes with high aspect ratio in the aluminum nitride substrate, so that the 3D IC aluminum nitride ceramic interposer can be prepared.